WO 2006090328 provides a data processing circuit with a test device with a buffer for information from cache coherence requests from processing elements that are coupled to a shared memory. Typical examples of a cache coherence request are snoop request signals issued to determine whether inconsistent copies of data are present in different cache circuits, invalidation signals for selected cache lines, update signals for data in cache lines etc. The circuit of WO 2006090328 may be a circuit that actually contains such a shared memory circuit and a plurality of processing elements with cache circuits or it may be a circuit that simulates the operation of a circuit with a plurality of processing elements that each comprise a cache circuit for caching data from the shared memory. A simulating circuit may be obtained for example by using a programmable computer programmed to perform operations corresponding to the operations of all of the processing elements.
The test device of WO 2006090328 is used during verification of the circuit, i.e. when it is investigated whether the circuit will not malfunction under extreme circumstances. The test device is designed to stress the circuit by issuing additional cache coherence requests. The information from cache coherence requests in the buffer is used to select addresses for which cache coherence requests will be generated and/or to predict times when there is expected to be a high number of cache coherence requests, in order to generate cache coherence requests selectively at such times. Accordingly, the test circuit is designed to use the content of the buffer to adapt the issuing of cache coherence requests.
The test device of WO 2006090328 contains a configuration register that makes it possible to switch the test device between different modes of operation. The modes may define a method of filtering cache coherence requests, i.e. selecting requests that may be ignored. For example the modes may include a burst mode wherein cache coherence requests from a selected address range are ignored to avoid that all requests are in the same range of addresses, another burst mode wherein cache traffic with contiguous addresses is generated, or a mode wherein cache coherence requests that are not of a specific desired type are ignored.
WO 2006090328 mentions various methods to decide on a switch between modes. For example the test device may react to the occurrence of too many invalidate requests by switching to a different mode. It is also noted that the operation mode can be defined by outside configuration. Thus, different stress situations may be simulated under control of the designer.
The circuit of WO 2006090328 has the disadvantage that it can only adapt the issue of simulated cache coherence requests reactively to previous cache coherence requests or by outside reconfiguration. In this way the test device may fail to provide maximum stress. It also does not make it possible to make use of periods of low stress.